This invention pertains to integrated circuits, and in particular BICMOS circuits which integrate bipolar and CMOS transistors on the same integrated circuit.
BICMOS circuits are often utilized to provide high output current utilizing bipolar transistors as the output devices, and low power operation by utilizing CMOS devices as the logic elements within the integrated circuit. FIG. 1 is a schematic diagram of a typical prior art BICMOS output buffer for providing an output signal on output lead 102 of a relatively high current carrying capability in response to a low current logic signal applied to input terminal 101. Such a circuit is also described in "Optimization and Scaling of CMOS-Bipolar Drivers for VLSI Interconnects" by De Los Santos et al. in IEEE Transactions on Electron Devices (1986) ED-33, No. 11, particularly with regard to FIG. 7.
In response to a logical one input signal applied to input terminal 101, P channel transistor 105 turns off, thereby removing base drive from bipolar pull up transistor 107, causing transistor 107 to turn off. Simultaneously, the high input signal on terminal 101 causes N channel transistor 106 to turn on, providing base drive to bipolar pull down transistor 109, thereby turning on transistor 109 and pulling down output terminal 102 to ground VSS. Conversely, in response to a logical zero input signal applied to input terminal 101, P channel transistor 105 turns on, thereby providing base drive to bipolar pull up transistor 107, causing transistor 107 to turn on, and pulling output terminal 102 to VDD. Simultaneously, the low input signal on terminal 101 causes N channel transistor 106 to turn off, removing base drive to bipolar pull down transistor 109, thereby turning off transistor 109.
The output voltage available on output terminal 102 can be as high as VDD-VBE (107), ignoring the voltage drop across N channel transistor 105, and can fall as low as VSS+VBE(109), ignoring the voltage drop across P channel transistor 106. For example, for the output signal available on output terminal 102 to be low (close to VSS), bipolar pull down transistor 109 must be turned on. This means that the base-emitter voltage of transistor 109 (VBE(109)), and therefore the voltage on output lead 102, is approximately 0.7 volts, since the voltage on the collector of output pull down transistor 109 cannot be less than the voltage on its base. Similarly, for the output signal available on output terminal 102 to be high (close to VDD), bipolar pull up transistor 107 must be turned on. This means that the base-emitter voltage of transistor 107 (VBE(107)) is approximately 0.7 volts and the voltage on output terminal 102 is approximately VDD-0.7 volts.
Thus, output voltage swing of circuit 100 is reduced by 1.4 volts relative to the desired swing of VDD-VSS. This is a major disadvantage, particularly when one considers that it is desired to use relatively low values of VDD with advanced BICMOS technologies.
In order to improve the switching speed of bipolar output transistors 107 and 109, N channel MOSFET transistors 108 and 110 are included in order to discharge the bases of bipolar output transistors 107 and 109, respectively, when they are to turn off. However, the inclusion of base discharge transistors 108 and 110 does not improve the fact that the output voltage available on output terminal 102 cannot be greater than VDD-VBE(107) nor be less than VSS+VBE(109).
FIG. 2a is a schematic diagram of another prior art BICMOS output buffer circuit 200, which is described in "A BiCMOS Logic Gate with Positive Feedback" by Nishio et al. in IEEE International Solid State Circuits Conference (1989), particularly with regard to Nishio's FIG. 1a. In circuit 200, base discharge transistors 108 and 110 of FIG. 1 are eliminated, and the base of pull up transistor 207 is connected to its emitter via resistor 208. Similarly, the base of pull down transistor 209 is connected to its emitter via resistor 210. By utilizing resistors 208 and 210, circuit 200 allows the output voltage available on output terminal 202 to fall as low as VSS, and rise as high as VDD. However, without the presence of base discharge transistors 108 and 110 of FIG. 1, the bases of output transistors 207 and 209 must be discharged through resistors 208 and 210, which increases the time required to discharge the bases of transistors 207 and 209, and thus increases the switching time of BICMOS output buffer 200. Another disadvantage of the prior art circuit of FIG. 2a is that resistors such as resistors 208 and 210, when fabricated in an integrated circuit, require a relatively large amount of surface area, thereby reducing the density of the integrated circuit, increasing cost.
Another prior art circuit is shown in FIG. 2b, and is described by Nishio et al., described above, particularly with reference to Nishio's FIG. 2a. However, this prior art circuit causes a severe penalty in integrated circuit density, because two different types of devices, both transistors and resistors are required in order to discharge the bases of the output pull down transistors while providing a wide output voltage swing.
Thus, two problems have been encountered in circuits which combine CMOS logic and bipolar output transistors: slow switching speed and limited output voltage swing. Adding discharge transistors such as the transistors 108 and 110 as shown in FIG. 1 solves the slow switching speed problem. However, the limited voltage swing is still a problem. Adding resistors, as shown in FIG. 2, solves the voltage swing problem. However, the slow switching speed is still a problem. Furthermore, using resistors introduces a new problem: resistors are physically bulky and, as circuits get smaller, this is an important consideration. Using a combination of discharge transistors and resistors solves both the switching speed and the limited output voltage swing problems. However, the bulky resistors are still a problem, and now the device is even more complex and physically bulky than if only the bulky resistors were used. In addition, as complexity increases so does cost. Therefore, there is a need for a way to solve both the switching speed and the voltage speed problems without introducing either bulk or complexity.